1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a C-BiCMOS (Complementary-BiCMOS) semiconductor device.
2. Description of the Background Art
FIGS. 17 to 21 are cross-sectional views of a conventional BiCMOS semiconductor device in sequence of fabrication.
A p type silicon substrate 1 is prepared, and n type high concentration buried layers 2 and a p type high concentration buried layer 3 are formed in the p type silicon substrate 1. An n.sup.- type epitaxial layer 4 is grown over the top surface. Selective impurity implantation by means of a resist mask (not shown) and heat treatment are carried out to selectively form a p well layer 6 and an n well layer 5 in an upper surface of the epitaxial layer 4. The epitaxial layer 4 is left as it is in a region wherein a bipolar transistor is to be formed later.
An LOCOS (local oxidation of silicon) process is performed by means of a nitride film mask (not shown) to form isolating oxide films 100. Before the LOCOS process, impurities for a channel-cutting p.sup.+ diffusion layer to isolate transistors from each other, for example boron, are implanted to form channel cut layers 7. The isolating oxide films 100 are formed to cover the channel cut layers 7. A collector wall layer 8 is formed by implantation of n type impurities of high concentration and heat treatment as shown in FIG. 17.
Next, MOS transistors are fabricated in the process steps described below. Initially, an oxide film and a polyorystalline silicon film for gate electrodes are formed on the semiconductor surface. Thereafter, n type impurities of high concentration are introduced into the polycrystalline silicon film, and patterning is performed by means of a resist mask (not shown), so that gate oxide films 110 and gate electrodes 200 are formed. To form n.sup.- layers 9 for the LDD of an NMOS transistor, ions of n type impurities of low concentration are selectively implanted into the p well region 6. During the ion implantion process, a resist mask not shown) covers the region wherein the bipolar transistor is to be formed or the epitaxial layer 4 and a region wherein a PMOS transistor is to be formed or the n well layer 5. An oxide film is formed all over. When dry etching is carried out all over, the oxide film is left only in gate side wall portions, so that side walls 120 are formed.
Subsequently, n type impurities of high concentration and p type impurities of high concentration are selectively implanted in series by means of a resist mask (not shown), and heat treatment is performed. This provides source-drain layers 10 of the NMOS transistor, the n.sup.- layers 9 for the LDD of the NMOS transistor, and source-drain layers 11 of the PMOS transistor. An oxide film 130 is then deposited all over, as shown in FIG. 18.
Next, process steps of fabricating the bipolar transistor are carried out. Initially, the oxide film 130 is selectively etched away by using a resist mask (not shown) until the surface of the epitaxial layer 4 is exposed. Polycrystalline silicon is formed all over. Ion implantation is performed with p type impurities of high concentration, and an oxide film is formed. At this time, the oxide film is deposited at low temperatures of below 500.degree. C. so that the p type impurities are not diffused into the epitaxial layer 4 from the polycrystalline silicon.
By using a resist mask (not shown), the oxide film and polycrystalline silicon film are selectively removed by etching and are then patterned, to form base electrodes 210 and insulating layers 140 such that the epitaxial layer 4 is exposed.
The surface of the epitaxial layer 4 is thinly oxidized to form an oxide film 150. Ions of p type impurities for an intrinsic base are implanted into the epitaxial layer 4 through the oxide film 150. Heat treatment is succeedingly carried out to form external base layers 12 and an intrinsic base layer 13, as shown in FIG. 19.
An oxide film is formed all over, and dry etching is performed on the oxide film, whereby the intrinsic base layer 13 is exposed in a region 300. Emitter base electrode isolating oxide films 160 are formed on the intrinsic base layer 13, as shown in FIG. 20.
Layer insulating films 400 are deposited, and etched selectively to open via holes. By aluminium wiring are formed a collector electrode 500, an emitter extracting electrode 501, a base extracting electrode 502, a source extracting electrode 503 of the NMOS transistor, a drain extracting electrode 504 thereof, a source extracting electrode 505 of the PMOS transistor and a drain extracting electrode 506 thereof, as shown in FIG. 21.
In the conventional semiconductor device having the above-mentioned constructions, a portion in which an electrode connected to the source-drain layer is formed has a large size. The conventional semiconductor device, hence, has a problem in that it is difficult to reduce the size of the devices or transistors. To solve the problem, it has been proposed that the electrode connected to the source-drain layer is formed of a polycrystalline semiconductor. However, the connection of the polycrystalline semiconductor to both of the source and drain layers causes electric conductivity to deteriorate. The problem of more complicated process steps remains unsolved for a C-BiCMOS semiconductor device including a large number of different devices.